1. Field of Invention
The present invention relates to a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof; particularly, it relates to such DMOS device and manufacturing method thereof wherein electrostatic discharge (ESD) effect is mitigated.
2. Description of Related Art
Lateral double diffused metal oxide semiconductor (LDMOS) device and double diffused drain metal oxide semiconductor (DDDMOS) are typical high voltage devices, which are both referred to as DMOS devices. FIGS. 1A-1B show a cross-section view and a top view of a prior art LDMOS device 100 respectively. And FIGS. 2A-2B show a cross-section view and a top view of a prior art DDDMOS device 200 respectively. As shown in FIGS. 1A-1B, a field oxide region 12 is formed in a P-type substrate 11, wherein the field oxide region 12 for example is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure, the latter being shown in FIG. 1A. The LDMOS device 100 includes a gate 13, an N-type high voltage well 14, an N-type source 15, an N-type drain 16, a P-type body region 17, and a P-type body electrode 18. The N-type high voltage well 14, the N-type source 15 and the N-type drain 16 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13 and the field oxide region 12, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 17 and the P-type body electrode 18 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13 and the field oxide region 12, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. The source 15 and the drain 16 are below the gate 13 and at different sides thereof respectively. In the LDMOS device 100, part of the gate 13 is located on the field oxide region 12. FIG. 1A is a cross-section taken in a lateral direction along a cross-section line AB indicated in the top view FIG. 1B. Referring to FIG. 1B, in a vertical direction, a conductive layer 19 connects both the source 15 and the body electrode 18, such that the source 15 and the body region 17 are kept at a same voltage level, such as a ground level.
FIGS. 2A-2B show the cross-section view and the top view of the prior art DDDMOS device 200 respectively. The DDDMOS device 200 is different from the aforementioned LDMOS device 100 in that, a gate 23 of the DDDMOS device 200 is entirely on an upper surface of a P-type substrate 21 with no part on a field oxide region. The DDDMOS device 200 includes the gate 23, an N-type high voltage well 24, an N-type source 25, an N-type drain 26, a P-type body region 27, and a P-type body electrode 28. The N-type high voltage well 24, the N-type source 25 and the N-type drain 26 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 23, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The P-type body region 27 and the P-type body electrode 28 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 23, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. The source 25 and the drain 26 are below the gate 23 and at different sides thereof respectively. Referring to FIG. 2B, in a vertical direction, a conductive layer 29 connects both the source 25 and the body electrode 28, such that the source 25 and the body region 27 are kept at a same voltage level, such as the ground level.
The LDMOS and DDDMOS devices are DMOS devices. In general applications such as in an ESD test or actual operation, when the drain is electrically connected to a high voltage, especially an electrostatic voltage with a relatively high level, a very high electric field is formed at the end of the DMOS device, and the lateral channel between the source and the drain at the end of the DMOS device in the vertical direction often is not fully conductive, so a breakdown usually occurs at an end of the DMOS device in the vertical direction, which may damage the DMOS device. The prior art DMOS devices have limited capability of sustaining the ESD, and the application range of the DMOS devices is limited, because the end of the DMOS device in the vertical direction can not sustain the high electrostatic voltage and tends to breakdown.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DMOS device and a manufacturing method thereof, wherein the ESD effect of the DMOS device is mitigated, so that the DMOS device may have a broader application range.